Highly integrated semiconductor circuits are increasingly important, particularly in the field of producing battery operated devices such as cell phones, portable computers such as laptops, notebook and PDAs, wireless email terminals, MP3 audio and video players, portable wireless webbrowsers and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art, such storage may take the form of dynamic memory in which arrays of cells are provided, each cell is a storage capacitor formed with an adjacent access transistor. Dynamic memory of DRAM offers excellent density and required minimum silicon area, and is often provided as fast access memory for a processor, such as a first level cache memory or scratchpad memory. In the prior art it is known to produce these DRAMs as stand alone integrated circuits using dedicated semiconductor process techniques that are specifically optimized to produce space and power efficient DRAM devices.
As semiconductor process technology advances have occurred, recently the fabrication technology has enabled the DRAM to be incorporated into large, highly integrated ICs, sometimes called “SOCs” or “systems on a chip”. Typical applications for these embedded DRAMs or “e-DRAM” include for use as fast memory adjacent a processor such as cache memory, as fast scratchpad memory, or to reduce the need for or totally replace the discrete DRAM devices in systems where space is at a premium.
In conjunction with the increasing use of DRAMs embedded with various other logic circuitry on a single integrated circuit, process technologies for manufacturing of integrated circuits continue to shrink. As the scaling of the dimensions of CMOS integrated circuitry gets smaller, certain dominant problematic effects become increasingly dominant. The resistance of the fine wires used to fabricate control lines increases, as the amount of metal or conductive polysilicon used to produce the lines decreases along with device size. This increased resistance results in signal distortion in control signals that run for substantial distances across a device, and especially for control signals that see many loads.
The increased processing power and parallelism in modern processors has lead to increased data word width in many designs. While early microprocessors were only four or eight bits wide, current data word widths are 32 or even 64 bits wide. This width drives many functions to be arranged in a wide fashion and in particular leads to wide memory arrays. For a 64 bit wide DRAM, the array may have 64 columns. The data word width therefore tends to push the length of the control signals, which must traverse across all 64 columns to longer lengths.
FIG. 1 depicts a typical prior art memory cell 11. For a dynamic memory cell such as is commonly used, an access transistor (Ts) couples a data line (DL), sometimes referred to as a bit line or “BL” in response to control voltage on a gate terminal of the access transistor coupled to the wordline WL, to a storage capacitor (Cs) which is coupled between the access transistor and a reference or supply voltage (Vs). The voltage used as the potential for the storage capacitor can be a ground or a positive voltage, depending on the particular design of the DRAM, as is known in the art. The gate of the access transistor Ts is coupled to one of a plurality of lines called word lines (WL), often referred to as row lines or rows. A typical DRAM will have many thousands of the cells 11 depicted. The cells will be arranged in one or more arrays and typically the bit lines or data lines DL will be arranged in a plurality of spaced columns, the word lines or row lines will be arranged in a plurality of rows. The storage capacitor may be fabricated in many ways. Although single transistor memory storage cell is depicted in FIG. 1, many other storage cells are known in the art including two transistor and even static RAM cells with six transistors. In the prior art for DRAM cells, planar capacitors have been used, more recently crown capacitors formed above the access transistors in insulating and metal layers have been used to further increase the density (number of bits per unit of silicon area) of the arrays. Alternate implementations where the capacitors are formed as part of a trench formed into the substrate adjacent the access transistors are known in the art and are likewise used to increase capacity per silicon area. In addition, various processing techniques are known to increase the capacitance of the cells, including as but one example hemispherical grain (HSG) polysilicon material, and other materials. Irrespective of the type of storage cell used, the significant feature is that the memory has an array of storage cells coupled to word lines and data lines by one or more access transistors,
The storage capacitor Cs of FIG. 11 may be used to hold a charge representing a logical data value. The voltage stored may be assigned a logical ‘1’ or a logical ‘0’ depending on the design approach used for the particular DRAM. The storage capacitor Cs is written by a control circuit coupling a data value for storage onto the data line DL while the access transistor Ts for the particular cell is simultaneously activated by placing the appropriate voltage on the control gate, that is, the word line WL associated with the cell 11 has a control voltage on it. To read the value, the access transistor is activated while no voltage or a simple bias level is placed on the data line DL and the capacitor discharges through the access transistor to place a stored voltage on the data line. This small voltage is then coupled to a sense amplifier where the level is sensed and amplified to the appropriate voltage representing a logical value; this logic voltage (a data value) is then coupled through I/O circuitry connected to the data line DL to make the read data available for use. To write the cell, a strong voltage is placed on the bit or data line DL and the access transistor is then activated using the access transistor by placing an active voltage on the word line WL. The capacitor is then charged to the proper voltage and when the access transistor is then disabled, the charged capacitor stores the appropriate value until the access transistor allows the capacitor to discharge in a subsequent read operation.
Because the storage capacitor Cs has an inherent leakage current, the storage cell 11 must be periodically refreshed by the control circuitry. The refresh cycle may be controlled by an external processor as is known in the art. More often in current products, an on board controller provided as part of the control circuitry will periodically refresh the storage capacitors (called “self-refresh” or “auto-refresh”). The refresh is a read write-back cycle that reads the stored values from a plurality of cells which require refreshing based on the time that has passed since the last refresh or access cycle, the data is read out, amplified by the sense amplifiers, and written back into the cells. Because the storage cells of a one transistor or 1T cell such as 11 require refreshing to maintain a stored value, the memory implemented using such cells is referred to as “dynamic” memory. Dynamic memory requires more control circuitry than a static memory, such as an SRAM, but the small physical size of the DRAM cell allows many more bits of storage to be implemented per unit of silicon area than is possible for a corresponding SRAM cell. Nonvolatile memory may also be used, such as EEPROM, FLASH, and the like; these memories also require additional control circuitry and the cells are sometimes larger in area than the DRAM cell 11.
FIG. 2 depicts in a plan view a block diagram of a DRAM array of the prior art using memory cells such as the one illustrated in FIG. 1. In DRAM 31, a plurality of memory cell arrays 35 is provided each having a plurality of memory cells 11 inside (not visible in the portion depicted). The memory cells are arranged as columns, with each column being associated with one bit of a data word, the I/O buffers 39 couple the data lines (not shown) which run in a columnar direction, to a data bus. Wordline decoders 33 activate the particular word line associated with a row of the memory cells 11 within the arrays 35 responsive to an address value received from outside. Each array of cells is coupled to a sense amplifier which receives two data lines, usually called bit line or BL and a complementary bit line or BL_. In FIG. 2 a single memory bank is shown so only one pair of bit lines is coupled for each column. Control logic 41 provides the various signals to the sense amplifiers 37 and the I/O buffers 39 to cause the data presented at the I/O ports to be written to the appropriate row of memory cells, or, to cause stored data to be read from the appropriate row of memory cells to output data from the I/O buffers 39. All of these operations and the circuits required are well known in the art.
FIG. 3 depicts a plan view of a block diagram of a further prior art embodiment of a DRAM array which uses segmented bit lines or data lines to share the sense amplifiers between two banks of memory cells. In FIG. 3, DRAM array 51 includes a memory bank 0 which is an upper memory bank and has memory cell arrays 55 that include memory cells as shown in FIG. 1 arranged in rows and columns, each memory array 55 having a pair of bit lines or data lines BL, word line decoders 53 provide the appropriate voltage on the appropriate word line or row lines (not shown) for reading and writing an addressed row of memory cells. Sense amplifiers 57 are shared between the upper memory bank 0 and the lower memory bank 1. A second wordline decoder circuit 53 for bank 1 is depicted in the lower portion of the block diagram and this wordline decoder provides the required word line signals for addressing a row of memory cells in the memory arrays 59 of bank 1. The data lines or bit lines from bank 1 are also selectively coupled to the same sense amplifiers 57 for each column in an architecture known as “segmented” bit lines. Although only two memory banks are illustrated, many more may be provided. A complete DRAM of the prior art may include thousands or even millions of cells in a single device. I/O buffers 61 then provide the output data to a data bus, or input data from a data bus, to couple the DRAM array 51 to circuits outside the array.
In FIG. 2, a distance arrow 42 is shown running horizontally across the sense amplifiers 37 on either side of the control logic 41. This distance arrow illustrates that a control signal from control logic 41 to control each of the sense amplifiers (all of which are typically active for a read or write cycle of a selected row of the DRAM cells) has a length proportional to the number of columns in the array. Further, because each bit of a data word is coupled to a column, the width of a data word used in a DRAM array determines how wide the array becomes and thus, how long these lines must be. Also, the number of bits in the data word determines how many columns there are in the array and thus how many sense amplifiers are coupled to the control line, that is, the width of the data word is proportional to the number of loads on the control line. As the data word width increases, the number of loads on the control line for the sense amplifiers also increases.
The arrangements of DRAM cells shown in FIG. 2 and FIG. 3 may depict the major blocks of a typical DRAM integrated circuit. However increasingly DRAM circuits are being embedded into application specific integrated circuits (ASICs), so called SOCs or “System on a Chip” devices, custom integrated circuits and the like. FIG. 4 depicts, in one typical prior art arrangement, the major blocks of an ASIC IC 1 with an embedded DRAM block A. In addition to the embedded DRAM, IC1 includes I/O buffers, an embedded SRAM block B which may be used as a register file, for example, a microprocessor core which could implement a programmable processor, a digital signal processor (DSP), or other known processors such as a RISC machine and the like. In addition to these core or predetermined functions, a section of user defined logic is shown. In this area a designer may implement functions that optimize the circuit for a specific use, such as for a PDA, digital camera, cellphone, music player, radio, or other application as is known in the art. DRAM blocks embedded with other circuitry in an ASIC or SOC are typically referred to as “e-DRAM.”
The use of improved semiconductor processing makes embedding DRAM and other memory blocks more attractive in ASIC or semicustom IC manufacture. Improved isolation and buried layer techniques, coupled with advanced photolithographic techniques, make it possible to provide the smaller transistor sizes and capacitors required for the DRAM block in one portion of an integrated circuit, while processing a different portion of the integrated circuit to produce the larger transistors, and even analog components such as resistors, required for other applications, in a single piece of silicon. These advances make efficient and compact DRAM arrays even more important.
FIG. 5 depicts a schematic of a typical prior art sense amplifier 101 used with an array of memory cells such as the cell shown in FIG. 1. In FIG. 5, a precharge/equalization circuit 103 is depicted. This circuit is controlled by the control signal PRE_ and when active, couples a voltage Vpre (precharge voltage) to a pair of nodes labeled DL_IN and DLB_IN through MOS transistors MP4, MP3. In another mode of operation the precharge circuit acts as an equalization circuit, and couples these two nodes together through a pass gate MP5. In this manner, the voltage placed on the nodes DL_IN and DLB_IN can be equalized or raised to a predetermined pre-charge voltage to speed the sensing of the differential voltage presented to the sense amplifier during a sense operation.
The data lines DL and DLB (data line and data line bar, could also be called bit lines or BL) are coupled to the sense latch 109 by the pass gate transistors PG1 and PG2 in the signal pass blocks 105, 107. In this embodiment, PMOS transistors are used for pass gats PG1, PG2, although it is known in the art to use NMOS transistors or a CMOS pair of transistors for this function. When the sense amplifier is to receive data from the data lines, a control voltage is placed on control inputs PG_U (for 105) or PG_V (for 107) respectively, and the pass gate allows the very small voltage signal sensed from a memory cell coupled to the data line by the control circuit and the word line decoder to appear on the respective sense nodes DL_IN and DLB_IN. The latch formed from the cross coupled inverters of MP1, MN1, and MP2, MN2 then latches the small signal received and amplifies it to a full logic voltage level, which can then be observed by the I/O buffers coupled to the data lines.
The sense latch is only operated when enabled by the transistor MNA which is controlled by the control signal SAE on the gate of MNA. Each sense amplifier depicted in FIGS. 3 and 4 is the same and each one receives the same control signal SAE from the control logic circuitry. The control logic circuitry therefore includes buffers or line drivers that provide this signal to all of the sense amplifiers.
In operation, as is known in the prior art, several steps are taken to sense the voltage stored in the sense amplifier. The differential sensing operation can be made faster by first precharging the two inputs of the differential sense amplifier made of the data latch 109 to a common mid range voltage, such as Vdd/2. Signal PRE_ is used to cause the MOS transistors MP4 and MP3 to be active to pre-charge the nodes DL_IN and DLB_IN to this voltage, which may be less than the positive supply voltage for the array, for example. Transistor MP5 further equalizes the two nodes to be sure the voltage is the same at both inputs to the differential sense amp. After the two nodes DL_IN and DLB_IN are pre charged, one of the two pass gates PG1 and PG2 will be activated, depending on the row and column address of the cell to be read. The selected pass gate will couple the small voltage sensed from the memory cell onto the respective sense node DL_IN or DLB_IN; the other node will remain at its precharged voltage due to parasitic capacitance in the circuit.
Finally the sense amplifier will be enabled by a pulse from the control circuitry on input SAE, which causes the enable transistor MNA to couple the sense amplifier latch 109 to a ground or other voltage supply (this could also be negative, for example) to allow current to flow through transistors MP1 MN1 MP2 MN2. Since one of the inputs DL_IN or DLB_IN will be greater than or less than a threshold potential for one of the transistors, while the other input is at an intermediate value, the latch 109 will latch that input value, Because the sense latch will amplify that input value due to the gain of the transistors in the latch, the small signal voltage sensed will be amplified to a full logic value for output to the I/O buffers. All of these operations and the circuit of FIG. 5 are well known in the art.
FIG. 6 depicts timing voltage diagram of the control pulse placed on control line SAE at the output of the control circuit, labeled “SAE control.” FIG. 6 also depicts what the pulse might look at when sampled at a prior art sense amplifier some distance from the control circuit in a second voltage diagram labeled “SAE sense amp.” Because the distance of the control line is long, and because there are many enable transistors (MNA in FIG. 5) coupled to the line (one for each sense amplifier in FIGS. 3 or 4), the signal can become distorted. To operate properly, either the driving circuitry in the central control logic circuits of FIG. 3, or 4, must be made quite large, or additional “repeater” circuitry must be provided. In order to keep the storage bit density per silicon area as high as possible, these approaches are typically avoided if at all possible. However, as the memory arrays become increasingly larger, and as the data word width becomes increasingly wide, the signal distortion problem will become worse and will require additional circuitry to correct. If the distortion remains, incorrect operation may occur if one or more sense amps do not in fact become enabled, while others which have less signal distortion are enabled.
Thus this prior art solutions requires added logic circuitry and layout area to address the distortion problem. A need thus exists for an improved sense amplifier circuit that maintains the layout efficiency and compactness of the prior art while offering an efficient solution to the distortion problem on the control lines, while still maintaining proper noise margins and ensuring correct data retention, fast access time, efficient operation and efficient use of silicon area.